A. Field of the Invention
This invention relates broadly to the field of digital computer systems. More particularly it relates to a method and apparatus for suspending a bus cycle of a processor and then restarting the cycle.
B. Prior Art
In all digital computing systems, the central processing unit (processor) is perhaps the most crucial element for determining the total system capacity and versatility. Generally, as digital computing has progressed, central processing units have become increasingly fast and capable of operating upon increasing amounts of data.
The development of more capable processors has encouraged digital computer designers to connect more and more input/output devices to the central processing unit. Also, increasing amounts of memory are also connected to the processor. Usually, these peripheral devices are connected to the processor along a bi-directional communication circuit called the system bus. The bus is capable of carrying data to and from the processor, the memory and the input/output devices. In a relatively recent development, additional processors may be connected to the bus.
This multiplicity of interconnected devices creates several problems. The first is that the operating speeds of the various LSI devices used to implement input/output devices vary greatly. For example, a serial port interface designed to operate with one vendor's microprocessor may be to slow to operate with another vendor's microprocessor. Some method needs to be found to allow a high speed implementation of a microprocessor with readily available low speed input/output devices.
Another is that more than one processor or input device may try to operate on a memory data structure at the same time. If data in a memory location is altered by a second processor or input/output device prior to the completion of a read/modify/write operation upon the location by the first processor, program synchronization will be lost and system operation severely degraded. Thus access to shared memory must be allocated and controlled in a systematic way between all input/output devices and the processors so as to avoid the overlap problem.
Although prior computing systems have used various methods in attempts to overcome these problems, they have not been completely successful. The methods currently used to prevent improper access to memory locations can result in the loss of processor operating time due to required initializations and established protocols. The various methods of allowing the input/output devices to communicate over the system bus also frequently result in losing available processing time. The same loss of processor time results from the methods used to interface relatively slow input/output devices with memory devices and the processors.
Copending patent application Ser. No. 534,720, filed Sep. 22, 1983, entitled "Retry Mechanism For Releasing Control Of A Communications Path In A Digital Computer System", now U.S. Pat. No. 5,021,038 assigned to the same assignee as the present invention, and the disclosure of which is hereby incorporated by reference, discloses a retry mechanism. In the system disclosed therein the possibility exists for a communications path interlock. In such instances where a communication path is interlocked and a processor attempts to use that path, what is called a RETRY response is asserted. Thus, in the disclosed system which describes a master-slave relationship, RETRY is asserted by a slave device which cannot immediately respond to a transaction. An example is a memory which has been locked by an interlock read command. As described in this copending application the then current master responds to a slave RETRY response by terminating the transaction. The disclosed system assumes that the processor is designed to accept the RETRY response and is able to act upon it. However, not every processor, particularly in the case of small microprocessors used on single board computers, is adapted to respond to a RETRY command. On the other hand, in a system where resources are shared it is a great benefit to have the ability to respond to a RETRY command by suspending the transaction then in process and picking it up again.